Clock signals may be propagated across an integrated circuit or from one integrated circuit to another integrated circuit to enable reliable data transfer from one point to another point. The propagation of clock signals and data signals generally has to satisfy certain timing constraints for reliable data transfers. Meeting such timing constraints may impose increasing challenges on clock distribution as clock frequencies increase and integrated circuit feature sizes shrink.
Clock distribution in a single clock domain may encounter growing challenges as the clock frequency of an integrated circuits increases and circuit feature sizes shrink. Use of multiple clock domains, each with its own clock frequency, may also encounter problems when data signals have to be propagated between clock domains. Violation of the set-up and hold times of sequential circuit elements such as flip-flops in the receiving clock domain may result in metastable behavior of the sequential circuit elements (i.e., the output of the element can hover between a logic zero and a logic one state for longer than a clock cycle). Such metastable behavior may result in the loss of data and/or data instability.
Data signals may be transferred asynchronously (i.e., data is transferred at irregular intervals without using a common clock) within an integrated circuit or between integrated circuits. Reliable data transmission is generally needed when the data is asynchronously transferred. FIG. 1 depicts an asynchronous data transfer scenario between a first system 2, controlled by a first clock 3, that transmits N-bit data words 4 to a second system 5, controlled by a second clock 6. The first clock 3 may be propagated between systems 2, 5 as a separate clock signal 7 or may be encoded in the data words. The systems 2, 5 may represent separate chips or separate units within an integrated circuit employing asynchronous clocks 3, 6 (i.e., the two clocks may have a varying phase relationship or may be unrelated). The propagation of the clock and the data signals generally have to satisfy certain timing constraints to achieve reliable data transfer between the two systems. Generally each data word 4 transmitted by system 2 should be received by system 5 exactly once. Further, system 2 generally has to keep the data word 4 stable while flip-flops in system 5 sample the data word.
A clock domain may be defined as that part of an integrated circuit having a group of sequential circuit elements driven by a common clock. Generally, sequential circuit elements driven by clocks having variable phase and time relationships may be partitioned into a plurality of clock domains. FIG. 2, depicts a CPU or ASIC design incorporating multiple clock domains 10, 12 on an integrated circuit 14. A plurality of clock domains may be employed for a variety of reasons including relaxed timing constraints, increased performance and reduced power consumption.
The CPU or ASIC may employ an input/output (I/O) interface 11 driven by a clock whose frequency may be defined by an industry standard (e.g., PCI Express). Such I/O clock frequencies may be limited to a few hundred megahertz. Other portions of the CPU or ASIC may be designed to operate at very high clock frequencies, typically several gigahertz, for performance reasons. Additionally, portions of the CPU or ASIC may be driven by separate clocks to ease the problem of clock skew across the CPU or ASIC. When a signal 16 crosses clock domains, it generally has to be properly handled to avoid the loss of signal values and/or avoid signal instability in the receiving clock domain.
Generally, each clock domain may have several sequential circuit elements such as flip-flops and/or latches. If the data input to a sequential element changes too close to a clock edge, the sequential element may become metastable, resulting in an output state that cannot be reliably used. Thus, the proper operation of the clocked flip-flop may depend on the input being stable for a certain period of time before and after the clock edge (i.e., the set-up and hold times of the sequential element). If the setup and hold times are not met, the output of the flip-flop may take a very long time to reach a valid logic level (referred to as unstable behavior or metastability).
FIG. 3A illustrates a situation that may lead to a metastable output on a flip-flop when a signal is propagated between two clock domains 22, 28. A signal D may be propagated by flip-flop 20 in a clock domain 22, driven by a clock 24, to a flip-flop 26, in a receiving clock domain 28, driven by a clock 30. The flip-flop 26, driven by the clock 30 may sample the output 32 of the flip-flop 20 while the output 32 is changing (for example, at the rising edge of clock 24 and falling edge of output 32) resulting in metastability. The propagation of the signal 32 into the clock domain 28 may be considered an asynchronous signal, i.e., no constant phase and time relationship exists between the clock 24 and the clock 30.
FIG. 3B depicts a timing diagram for the circuit of FIG. 3A. Waveform 35 may be the CLKA input to flip-flop 20. Waveform 36 may be the output 32 of flip-flop 20 being propagated from clock domain 22 to clock domain 28. Waveform 37 may be the CLKB signal applied to the clock input 30 of synchronizer flip-flop 26. Waveform 38 may be the resulting output signal 34 of synchronizer flip-flop 26. Because the input signal 36 of synchronizer flip-flop 26 may be changing when the clock edge 39 occurs, the output 38 of the synchronizer flip-flop 26 may become metastable. Generally metastability cannot be avoided, but proper handling of the metastable signal may enable proper circuit operation.
One current approach to handling a data signal crossing clock domains may involve the use of an asynchronous interface. FIG. 4 depicts the use of a second synchronizer flip-flop 40 that may reduce the effects of any metastable behavior of flip-flop 26. The second synchronizer flip-flop 40 may create a more stable (i.e., less risk of metastability) signal 42 that may be used in the downstream logic 44. However, use of a second synchronizer flip-flop 40 may introduce additional latency. For example, two or more clock cycles (i.e., two or more synchronizer flip-flops) may be necessary to transfer the data from the clock domain 22 to the clock domain 28 resulting in lower performance. Data may also be transferred across clock domains by storing the data in a fifo (first-in, first-out buffer) that may employ a control signal passing through two flip-flops. The two flip-flops may buy enough time to reduce the risk of metastability but may also result in increased signal latency.
What is needed is a method for reliably transferring data between clock domains that does not use asynchronous interfaces. What is further needed is a method for transferring data between clock domains that minimizes latency.